BUSY=Val_0x0, DCOL=Val_0x0, TXE=Val_0x0, TFNF=Val_0x0, RFNE=Val_0x0, RFF=Val_0x0, TFE=Val_0x0
Status Register
| BUSY | SPI Busy Flag. When set, indicates that a serial transfer is in progress; when cleared indicates that the SPI is idle or disabled. 0 (Val_0x0): SPI is idle or disabled 1 (Val_0x1): SPI is actively transferring data |
| TFNF | Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. 0 (Val_0x0): Transmit FIFO is full 1 (Val_0x1): Transmit FIFO is not full |
| TFE | Transmit FIFO Empty. When the transmit FIFO is completely empty, this bit is set. When the transmit FIFO contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. 0 (Val_0x0): Transmit FIFO is not empty 1 (Val_0x1): Transmit FIFO is empty |
| RFNE | Receive FIFO Not Empty. Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty. This bit can be polled by software to completely empty the receive FIFO. 0 (Val_0x0): Receive FIFO is empty 1 (Val_0x1): Receive FIFO is not empty |
| RFF | Receive FIFO Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. 0 (Val_0x0): Receive FIFO is not full 1 (Val_0x1): Receive FIFO is full |
| TXE | Transmission Error. Set if the transmit FIFO is empty when a transfer is started. This bit can be set only when the SPI is configured as a slave device. Note: LPSPI supports Master mode only. The high-speed SPIs support Master and Slave modes. For more information, see Section SPI Overview. Data from the previous transmission is present on the TXD line. This bit is cleared when read. 0 (Val_0x0): No Error 1 (Val_0x1): Transmission Error |
| DCOL | Data Collision Error. Relevant only when the SPI is configured as a master device. This bit is set if slave select input is asserted by other master, when the SPI master is in the middle of the transfer. This informs the processor that the last data transfer was halted before completion. This bit is cleared when read. 0 (Val_0x0): No Error 1 (Val_0x1): Transmit Data Collision Error |